? semiconductor components industries, llc, 2017 january, 2017 ? rev. 2 1 publication order number: ncp1589a/d ncp1589a, ncp1589b low voltage synchronous buck controller the ncp1589a/b is a low cost pwm controller designed to operate from a 5 v or 12 v supply. this device is capable of producing an output voltage as low as 0.8 v. this device is capable of converting voltage from as low as 2.5 v. this 10?pin device provides an optimal level of integration to reduce size and cost of the power supply. features include a 1.5 a gate driver design and an internally set 300 khz or 600 khz oscillator. in addition to the 1.5 a gate drive capability, other efficiency enhancing features of the gate driver include adaptive non?overlap circuitry. the ncp1589a/b also incorporates an externally compensated error amplifier. protection features include programmable short circuit protection and undervoltage lockout (uvlo). features ? v cc range from 4.5 v to 13.2 v ? 300 khz and 600 khz internal oscillator ? boost pin operates to 30 v ? voltage mode pwm control ? precision 0.8 v internal reference ? adjustable output voltage ? internal 1.5 a gate drivers ? 80% max duty cycle ? input under voltage lockout ? programmable current limit ? this is a pb?free device applications ? graphics cards ? desktop computers ? servers / networking ? dsp & fpga power supply ? dc?dc regulator modules dfn10 case 485c marking diagram pin connections 1589x = specific device code x = a or b a = assembly location l = wafer lot y = year w = work week = pb?free device 1 boot 10 pgood 2 lx 3 ug 4 lg 9 vos 8 fb 7 comp/disb (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. www. onsemi.com 5 gnd 6 v cc (note: microdot may be in either location) ncp1589amntwg dfn10 (pb?free) 3000 / tape & reel ncp1589bmntwg 1589x alyw ncp1589amntxg ncp1589bmntxg
ncp1589a, ncp1589b www. onsemi.com 2 figure 1. typical application diagram boot ug lx vcc gnd fb vos lg pgood v in = 2.5 v ? 20 v v cc = 4.5 v ? 13.2 v 0.1 f 4.7nf 2x1800 f 2.2 1 h 1500 f 1.02k r4 3.878k c3 0.014 f 1.02k r3 74.2 r1 4.12k c2 0.007 f r2 17.08k c1 0.0015 f 1 f comp/disb rocset ntd4806 ntd4809 3x22 f 1500 f 2x0.22 f v bst = 4.5 v ? 15 v gnd vout 1.65 v r9 r10 figure 2. detailed block diagram por uvlo pwm out latch 7 boot ug lx lg gnd clock ramp osc osc fb vocp fault fault fault soft start vos pgood monitor ov and uv pgood 0.8 v (v ref ) 0.8 v (v ref ) comp/disb + ? + ? q r s 8 9 10 + ? + ? vcc 2 v vcc 10% of v ref 25% of v ref 6 1 3 2 4 5 + ?
ncp1589a, ncp1589b www. onsemi.com 3 pin function description pin no. symbol description 1 boot supply rail for the floating top gate driver. to form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to boot pin). connect a capacitor (c boot ) between this pin and the lx pin. typical values for c boot range from 0.1 f to 1 f. ensure that c boot is placed near the ic. 2 lx switch node pin. this is the reference for the floating top gate driver. connect this pin to the source of the top mosfet. 3 ug top gate mosfet driver pin. connect this pin to the gate of the top n?channel mosfet. 4 lg bottom gate mosfet driver pin. connect this pin to the gate of the bottom n?channel mosfet. 5 gnd ic ground reference. all control circuits are referenced to this pin. 6 vcc supply rail for the internal circuitry. operating supply range is 4.5 v to 13.2 v. decouple with a 1 f capaci- tor to gnd. ensure that this decoupling capacitor is placed near the ic. 7 comp/disb compensation pin. this is the output of the error amplifier (ea) and the non?inverting input of the pwm comparator. use this pin in conjunction with the fb pin to compensate the voltage?control feedback loop. pull this pin low for disable. 8 fb this pin is the inverting input to the error amplifier. use this pin in conjunction with the comp pin to com- pensate the voltage?control feedback loop. connect this pin to the output resistor divider (if used) or directly to v out . 9 vos voltage offset sense 10 pgood power good output. pulled low if vos is 10% of 0.8 v v ref . absolute maximum ratings pin name symbol v max v min main supply voltage input vcc 15 v ?0.3 v bootstrap supply voltage input boot 35 v wrt/gnd 40 v < 100 ns 15 v wrt/lx ?0.3 v ?0.3 v ?0.3 v switching node (bootstrap supply return) lx 35 v 40 v for < 100 ns ?5 v ?10 v for < 200 ns high?side driver output (top gate) ug 30 v wrt/gnd 15 v wrt/lx 40 v for < 100 ns ?0.3 v wrt/lx ?2 v for < 200 ns low?side driver output (bottom gate) lg v cc + 0.3 v ?0.3 v ?5 v for < 200 ns feedback, vos fb, vos 5.0 v ?0.3 v comp/disb comp/disb 3.6 v ?0.3 v pgood pgood 7 v ?0.3 v maximum ratings rating symbol value unit thermal resistance, junction?to?ambient r ja 165 c/w thermal resistance, junction?to?case r jc 45 c/w operating junction temperature range t j 0 to 150 c operating ambient temperature range t a 0 to 70 c storage temperature range t stg ?55 to +150 c moisture sensitivity level msl 1 ? stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. this device is esd sensitive. use standard esd precautions when handling.
ncp1589a, ncp1589b www. onsemi.com 4 electrical characteristics (0 c < t a < 70 c; 4.5 v < [bst?phase] < 13.2 v, 4.5 v < bst < 30 v, 0 v < phase < 21 v, c tg = c bg = 1.0 nf, for min/max values unless otherwise noted.) characteristic conditions min typ max unit vcc voltage range 4.5 13.2 v boost voltage range 13.2 v wrt lx 4.5 30 v supply current quiescent supply current (ncp1589a) v fb = 1.0 v, no switching, v cc = 13.2 v 1.0 8.0 ma boost quiescent current v fb = 1.0 v, no switching 0.1 a undervoltage lockout uvlo threshold v cc rising 3.8 4.0 4.2 v uvlo threshold v cc falling 3.4 3.6 3.8 v uvlo hysteresis v cc rising or v cc falling 0.4 v switching regulator vfb feedback voltage (fb tied to comp. measure fb pin.) 0.7936 0.8 0.8064 v oscillator frequency (ncp1589a) 270 300 330 khz oscillator frequency (ncp1589b) 540 600 660 khz ramp?amplitude voltage 1.1 v minimum duty cycle 0 % maximum duty cycle 70 75 80 % lg minimum on time 500 ns error amplifier open loop dc gain (note 1) 70 80 db output source current output sink current v fb < 0.8 v v fb > 0.8 v 2.0 2.0 ma input offset voltage (note 1) ?2.0 0 2.0 mv input bias current 0.1 1.0 a unity gain bandwidth (note 1) 15 mhz disable threshold 0.6 0.8 v output source current during disable 10 40 a gate drivers upper gate source v cc = 5 v, vug ? vlx = 2.5 v 1.5 a upper gate sink 1.4 lower gate source 1.5 a lower gate sink v cc = 12 v 1.0 ug falling to lg rising delay v cc = 12 v, ug?lx < 2.0 v, lg > 2.0 v 12.4 18 ns lg falling to ug rising delay v cc = 12 v, lg < 2.0 v, ug > 2.0 v 12.4 18 ns soft?start soft?start time 3.0 7.0 ms power good output voltage logic low, sinking 4 ma 0.4 v ovp threshold to pgood output low ramp vos from 0.7 to 1.2. monitor when pgood goes low 0.88 1.0 v ovp threshold to part disable ramp vos from 0.8 to 1.2. monitor when outputs disable 1.0 1.2 v uvp threshold to pgood output low ramp vos from 800 mv to 500 mv. monitor when pgood goes low 0.65 0.72 v uvp threshold to part disable ramp vos from 800 mv to 500 mv. monitor when utputs stop switching 0.5 0.6 v overcurrent protection oc current source (note 1) sourced from lg pin, before ss 9.0 10 11 a 1. guaranteed by design but not tested in production.
ncp1589a, ncp1589b www. onsemi.com 5 typical characteristics 303 010 70 t j , junction temperature ( c) f sw , frequency (khz) 302 301 300 299 figure 3. oscillator frequency (f sw ) vs. temperature 543 542 541 540 539 0 20 406080 t j , junction temperature ( c) ocp threshold (mv) 020406080 t j , junction temperature ( c) i cc (ma) 5.3 5.0 4.7 4.4 3.5 figure 4. reference voltage (v ref ) vs. temperature figure 5. i cc vs. temperature 3.8 4.1 v cc = 12 v figure 6. ocp threshold at 55k vs. temperature 808 04080 t j , junction temperature ( c) v ref , reference (mv) 806 804 802 800 798 796 794 792 v cc = 5 v 20 30 40 50 60 20 60 ncp1589b ncp1589a
ncp1589a, ncp1589b www. onsemi.com 6 applications information over current protection (ocp) the ncp1589a/b monitors the voltage drop across the low side mosfet and uses this information to determine if there is excessive output current. the voltage across the low side mosfet is measured from the lx pin, and is referenced to ground. the over current measurement is timed to occur at the end of the low side mosfet conduction period, just before the bottom mosfet is turned off. if the voltage drop across the bottom mosfet exceeds the over current protection threshold, then an internal counter is incremented. if the voltage drop does not exceed the over current protection threshold, then the internal counter is reset. the ncp1589a/b will latch the over current protection fault condition only if the over current protection threshold is exceeded for four consecutive cycles. when the ncp1589a/b latches an over current protection fault, both the high side and low side mosfets are turned off. to reset the over current protection fault, the power to the vcc pin must be cycled. the over current threshold voltage can be externally, by varying the value of the rocset resistor. the rocset resistor is a resistor connected between the lg pin (low side mosfet gate) and ground. during startup, after the vcc and boot pins reach the under voltage lock out threshold, the ncp1589a/b will source 10 a of current out of the lg pin. this current will flow through the rocset resistor and produce a voltage that is sampled and then used as the over current protection threshold voltage. for example, if rocset is set to 10 k , the 10 a of current will yield a 100 mv threshold, and if the voltage drop across the low side mosfet exceeds 100 mv at the end of its conduction period, then an over current event will be detected. if the rocset resistor is not present, then the over current protection threshold will max out at 640 mv. the valid range for rocset is 5 k to 55 k which yields a threshold voltage range of 50 mv to 550 mv. internal soft-start to prevent excess inrush current during startup, the ncp1589a/b uses a calibrated current source with an internal soft start capacitor to ramp the reference voltage from 0 to 800 mv over a period of 4 ms. the softstart ramp generator will reset if the input power supply voltages reach the under voltage lockout threshold, or if the ncp1589a/b is disabled by having the comp pin pulled low. startup into a precharged load during a startup and soft start sequence the ncp1589a will detect a residual charge on the output capacitors and not forcefully discharge the capacitors before beginning the softstart sequence, instead, the softstart ramping of the output will begin at the voltage level of the residual charge. for example, if the ncp1589a/b is configured to provide a regulated output voltage of 2.5 v, the normal softstart sequence will ramp the output voltage from 0 to 2.5 v in 4.2 ms; however if the output capcitors already have a 1.2 v charge on them, the ncp1589a/b will not discharge the capacitors, instead the softstart sequence will begin at 1.2 v and then ramp the output to 2.5 v. power good the pgood pin is an open drain active high output pin that signals the condition of the vos (v oltage output sense) pin. pgood is pulled low during soft start cycle, and if there is a latched over current, over voltage, or under voltage fault. if the voltage on the vos pin is within 10% of vref (800 mv) then the pgood pin will not be pulled low. the pgood pin does not have an internal pull-up resistor. overvoltage protection if the voltage on the vos pin exceeds the over voltage threshold the ncp1589a/b will latch an over voltage fault. during an over voltage fault the ug pin will be pulled low, and the lg pin will be high while the until the voltage on the vos pin goes below v ref /2 (400 mv). the ncp1589a will continue drive the lg pin, lg will go high if vos exceeds 1 v and then go low when vos goes below 400 mv. the power to the ncp1589 must be cycled to reset the over voltage protection fault. under voltage protection if the voltage on the vos pin falls below the under voltage threshold after the soft start cycle completes, then the ncp1589a/b will latch an under voltage fault. during an under voltage fault, both the ug and lg pins will be pulled low. the power to the ncp1589 must be cycled to reset the under voltage protection fault.
ncp1589a, ncp1589b www. onsemi.com 7 figure 7. typical startup sequence v cc comp ug lg v out fb pgood internal uvlo fault ?0.7 v 1.45 v 700 mv 50 mv ocp program- mable 0.8 v normal ss uvlo por 4.0 v 3.6 v
ncp1589a, ncp1589b www. onsemi.com 8 figure 8. typical power good function u g l g 0.88v 0.4v 1.0v p good 0.88v 0.8v 0.72v 0.8v 0.6v vos overvoltage undervoltage feedback and compensation the ncp1589a/b allows the output voltage to be adjusted from 0.8 v to 5.0 v via an external resistor divider network. the controller will try to maintain 0.8 v at feedback pin. thus, if a resistor divider circuit was placed across the feedback pin to v out , the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 v at the fb pin. the same formula applies to the vos pin and the controller will maintain 0.8 v at the vos pin. v out r1 r4 fb figure 9. the relationship between the resistor divider network above and the output voltage is shown in the following equation: r 4 r 1 v ref v out v ref the same formula can be applied to the feedback resistors at vos. r 9 r 10 v ref v out v ref design example voltage mode control loop with type iii compensation converter parameters: input voltage: v in = 5 v output voltage: v out = 1.65 v switching frequency: 300 khz total output capacitance: c out = 3600 f total esr: esr = 6 m output inductance: l out : 1 h ramp amplitude: v ramp = 1.1 v ? + figure 10. c3 r3 r1 c1 c2 r2 v out v comp v ref e/a r4 a.. set a target for the close loop bandwidth at 1/6 th of the switching frequency. f cross_over : 50 khz
ncp1589a, ncp1589b www. onsemi.com 9 b.. output filter double pole frequency f lc 2.653 khz f lc : 1 2 l out c out c.. esr zero frequency: f esr 7.368 khz f esr : 1 2 c out c esr step 1: set a value for r1 between 2 k and 5 k r1 : 4.12 k step 2: pick compensation dc gain (r2/r1) for desired close loop bandwidth. v ramp : 1.1 v r2 : r1 v ramp v in f cross_over f lc r2 17.085 k step 3: place 1st zero at half the output filter double pole frequency. c2 : 2 l out c out r2 c2 7.024 10 ?3 f step 4: place 1st pole at esr zero frequency. c1 : c2 c2 r2 2 f esr 1 c1 1.542 10 ?3 f step 5: place 2 nd zero at the output filter double pole frequency. r3 : r1 f sw 2 f lc 1 r3 74.169 step 6: place 2 nd pole at half the switching frequency. c3 : 1 r3 f sw c3 0.014 f step 7: r4 is sized to maintain the feedback voltage to v ref = 0.8 v. r4 : v ref r1 v out v ref r4 3.878 k the component values for type iii compensation are: r1 = 4.12 k r2 = 17.085 k r3 = 74.169 r4 = 3.878 k c1 = 0.0015 f c2 = 0.007 f c3 = 0.014 f note: recommend to change values to industry standard component values.
ncp1589a, ncp1589b www. onsemi.com 10 package dimensions dfn10, 3x3, 0.5p case 485c issue e *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.64 1.90 0.50 0.55 10x 3.30 0.30 10x dimensions: millimeters pitch package outline ??? ??? ??? 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. for device opn containing w option, detail a and b alternate construction are not applicable. wet- table flank construction is detail b as shown on side view of package. b a 0.15 c top view side view bottom view pin one reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x detail b ?? ?? ?? on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1589a/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?
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